Method for Making Split Dual Gate Field Effect Transistor

ABSTRACT

A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No.200610023749.3, filed Feb. 6, 2006, commonly assigned, incorporated byreference herein for all purposes.

The following two commonly-owned co-pending applications, including thisone, are being filed concurrently and the other one is herebyincorporated by reference in its entirety for all purposes:

1. U.S. patent application Ser. No. 11/377,936, in the name of DeyuanXiao, Gary Chen, Tan Leong Seng, and Roger Lee, titled, “Split Dual GateField Effect Transistor,” (Attorney Docket Number 021653-015100US); and

2. U.S. patent application Ser. No. 11/377,236, in the name of DeyuanXiao, Gary Chen, Tan Leong Seng, and Roger Lee, titled, “Method forMaking Split Dual Gate Field Effect Transistor,” (Attorney Docket Number021653-019300US).

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH OR DEVELOPMENT

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISK

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a method for making a split dualgate field effect transistor. Merely by way of example, the inventionhas been applied to a logic system. But it would be recognized that theinvention has a much broader range of applicability.

Integrated circuits or “ICs” have evolved from a handful ofinterconnected devices fabricated on a single chip of silicon tomillions of devices. Current ICs provide performance and complexity farbeyond what was originally imagined. In order to achieve improvements incomplexity and circuit density (i.e., the number of devices capable ofbeing packed onto a given chip area), the size of the smallest devicefeature, also known as the device “geometry”, has become smaller witheach generation of ICs. Semiconductor devices are now being fabricatedwith features less than a quarter of a micron across.

Increasing circuit density has not only improved the complexity andperformance of ICs but has also provided lower cost parts to theconsumer. An IC fabrication facility can cost hundreds of millions, oreven billions, of dollars. Each fabrication facility will have a certainthroughput of wafers, and each wafer will have a certain number of ICson it. Therefore, by making the individual devices of an IC smaller,more devices may be fabricated on each wafer, thus increasing the outputof the fabrication facility. Making devices smaller is very challenging,as a given process, device layout, and/or system design often work downto only a certain feature size.

An example of such a limit is how to reduce the transistor leakagecurrent and improve the transistor drive current. For example, reducingthe source-drain voltage of a transistor can lower the active power, butdoing so often reduces the transistor drive current. The transistordrive current can be improved by reducing the threshold voltage andthinning the gate dielectric, but such actions often raise thetransistor leakage current.

From the above, it is seen that an improved method for making atransistor structure is desired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a method for making a split dualgate field effect transistor. Merely by way of example, the inventionhas been applied to a logic system. But it would be recognized that theinvention has a much broader range of applicability.

In a specific embodiment, the invention provides a method for making asemiconductor device with at least two gate regions. The method includesproviding a substrate region including a surface. Additionally, themethod includes forming a source region in the substrate region by atleast implanting a first plurality of ions into the substrate region andforming a drain region in the substrate region by at least implanting asecond plurality of ions into the substrate region. The drain region andthe source region are separate from each other. Moreover, the methodincludes depositing a gate layer on the surface and forming a first gateregion and a second gate region on the surface. The forming a first gateregion and a second gate region includes forming an insulation region onthe surface by at least removing a part of the gate layer, and the firstgate region and the second gate region are separated by the insulationregion. The first gate region is capable of forming a first channel inthe substrate region, and the first channel is from the source region tothe drain region. The second gate region is capable of forming a secondchannel in the substrate region, and the second channel is from thesource region to the drain region.

According to another embodiment of the present invention, a method formaking a semiconductor device with at least two gate regions includesproviding a substrate region including a surface. Additionally, themethod includes forming a source region in the substrate region by atleast implanting a first plurality of ions into the substrate region,and forming a drain region in the substrate region by at leastimplanting a second plurality of ions into the substrate region. Thedrain region and the source region are separate from each other.Moreover, the method includes depositing a gate layer on the surface andforming a first spacer region. The first spacer region is in contactwith the gate layer. Also, the method includes forming a second spacerregion, and the second spacer region is in contact with the gate layer.Additionally, the method includes removing at least a part of the gatelayer to form a first gate region, a second gate region, and aninsulation region on the surface. The first gate region and the secondgate region are separated by the insulation region.

According to yet another embodiment of the present invention, a methodfor making a semiconductor device with at least two gate regionsincludes providing a substrate region including a surface. Additionally,the method includes forming a source region in the substrate region byat least implanting a first plurality of ions into the substrate region,and forming a drain region in the substrate region by at leastimplanting a second plurality of ions into the substrate region. Thedrain region and the source region are separate from each other.Moreover, the method includes depositing a gate layer on the surface,and forming a first spacer region. The first spacer region is in contactwith the gate layer. Also, the method includes forming a second spacerregion, and the second spacer region is in contact with the gate layer.Additionally, the method includes removing at least a part of the gatelayer to form a first gate region, a second gate region, and aninsulation region on the surface. The first gate region and the secondgate region are separated by the insulation region. The first gateregion is associated with a first channel related to a first channellength, and the first channel length is equal to or shorter than 200 nm.The insulation region is associated with a width in a direction from thefirst gate region to the second gate region, and the width ranges from10 nm to 10,000 nm.

Many benefits are achieved by way of the present invention overconventional techniques. Some embodiments of the present inventionprovide a new method for making a new planar split dual gate transistordevice. Certain embodiments of the present invention provide a methodfor making dual gates that can be biased independently. For example, theindependent gate biases can provide dynamical control of the devicecharacteristics such as threshold voltage, sub-threshold swing, and/orthe saturation drain current. Some embodiments of the present inventioncan be used to make a device that significantly reduces transistorleakage current. Certain embodiments of the present invention provide amethod for making a device that has adjustable threshold voltage withoutvarying gate oxide thickness or doping profile.

Various additional objects, features and advantages of the presentinvention can be more fully appreciated with reference to the detaileddescription and accompanying drawings that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified method for making split dual gate field effecttransistor according to an embodiment of the present invention;

FIGS. 2(A) and (B) show a simplified method for forming shall trenchisolation for making split dual gate field effect transistor accordingto an embodiment of the present invention;

FIG. 3 shows a simplified method for forming doped well for making splitdual gate field effect transistor according to an embodiment of thepresent invention;

FIGS. 4(A) and (B) show a simplified method for forming gate region forsplitting for making split dual gate field effect transistor accordingto an embodiment of the present invention;

FIG. 5 shows a simplified method for forming LDD region and spacerregion for making split dual gate field effect transistor according toan embodiment of the present invention;

FIG. 6 shows a simplified method for forming heavily doped source regionand heavily doped drain region for making split dual gate field effecttransistor according to an embodiment of the present invention;

FIGS. 7(A), (B), and (C) show a simplified method for forming split dualgates for making split dual gate field effect transistor according to anembodiment of the present invention;

FIGS. 8(A), (B), and (C) show a simplified method for forming salicidelayer and insulation layer for making split dual gate field effecttransistor according to an embodiment of the present invention;

FIG. 9 shows a simplified method for forming inter-layer dielectriclayer for making split dual gate field effect transistor according to anembodiment of the present invention;

FIG. 10 shows a simplified method for forming contact layer for makingsplit dual gate field effect transistor according to an embodiment ofthe present invention;

FIGS. 11(A) and (B) show a simplified method for forming metal layer formaking split dual gate field effect transistor according to anembodiment of the present invention;

FIG. 12 shows a simplified method for forming passivation layer formaking split dual gate field effect transistor according to anembodiment of the present invention;

FIGS. 13(A) and (B) show a simplified method for making split dual gatefield effect transistor according to another embodiment of the presentinvention;

FIG. 14 is a simplified diagram for split dual gate field effecttransistor according to an embodiment of the present invention;

FIG. 15 is a simplified top-view layout diagram for split dual gatefield effect transistor according to another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a method for making a split dualgate field effect transistor. Merely by way of example, the inventionhas been applied to a logic system. But it would be recognized that theinvention has a much broader range of applicability.

FIG. 1 is a simplified method for making split dual gate field effecttransistor according to an embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims herein. The method 2100 includes the following processes:

-   -   1. Process 2110 for forming shallow trench isolation;    -   2. Process 2115 for forming doped well;    -   3. Process 2120 for forming gate region for splitting;    -   4. Process 2125 for forming LDD region and spacer region;    -   5. Process 2130 for forming heavily doped source region and        heavily doped drain region;    -   6. Process 2135 for forming split dual gates;    -   7. Process 2140 for forming salicide layer and insulation layer;    -   8. Process 2145 for forming inter-layer dielectric layer;    -   9. Process 2150 for forming contact layer;    -   10. Process 2155 for forming metal layer;    -   11. Process 2160 for forming passivation layer.

The above sequence of processes provides a method according to anembodiment of the present invention. Other alternatives can also beprovided where processes are added, one or more processes are removed,or one or more processes are provided in a different sequence withoutdeparting from the scope of the claims herein. Future details of thepresent invention can be found throughout the present specification andmore particularly below.

At the process 2110, one or more shallow trench isolations are formed.FIGS. 2(A) and (B) show a simplified method for forming shall trenchisolation for making split dual gate field effect transistor accordingto an embodiment of the present invention. These diagrams are merelyexamples, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications.

As shown in FIGS. 2(A) and (B), a starting semiconductor wafer 2210 isprovided. For example, the starting wafer 2210 includes silicon. Inanother example, the starting wafer 2210 includes a substrate region. Onthe starting wafer 2210, a silicon oxide layer 2220, a silicon nitridelayer 2230, and a silicon oxynitride layer are formed sequentially.Additionally, a trench 2240 is formed by etching part of the siliconoxynitride layer, the silicon nitride layer 2230, the silicon oxidelayer 2220, and the starting wafer 2210. The bottom surface and sidesurfaces of the trench 2240 are covered by an oxide layer 2250.Afterwards, the trench is filled by an oxide material 2260. For example,the oxide material 2260 includes HDP CVD oxide.

In one embodiment, the following processes are performed:

-   -   Wafer Start (P-type, 8-12 ohm-cm)    -   AA OXIDE DEPOSITION (Pad oxide 110 Å/920° C., 45 minutes dry O₂)    -   AA Nitride DEPOSITION 1625 Å (780° C., 10-40 Pa, SiH₂Cl₂/NH₃)    -   SiON DARC DEPOSITION 320 Å (DARC, 320 Å, helium based)    -   AA PHOTO/DUV (0.23±0.023 μm)    -   AA ETCH (0.22±0.025 μm)        -   (SiN/OXIDE etch chamber-1, Si etch chamber-2, 3500 Å, 80            degrees)    -   ST1 Liner OXIDE 200 Å (1000° C., dry O₂)    -   STI HDP (HDP STI5800, 5.8 KÅ)    -   STI CMP (4100±500 Å, Polish 2.5 KÅ/DIW-HF clean)

At the process 2115, one or more doped wells are formed. FIG. 3 shows asimplified method for forming doped well for making split dual gatefield effect transistor according to an embodiment of the presentinvention. This diagram is merely an example, which should not undulylimit the scope of the claims. One of ordinary skill in the art wouldrecognize many variations, alternatives, and modifications.

As shown in FIG. 3, the silicon oxynitride layer, the silicon nitridelayer 2230, and the silicon oxide layer 2220 are removed from the wafer2210. On the wafer 2210, another oxide layer 2310 is formed. Afterwards,in one example, an n-well is formed in the wafer 2210. Additionally, ananti-punch-through ion implantation is performed with p-type dopants,and a threshold-adjustment ion implantation is performed also withp-type dopants. In another example, a p-well is formed in the wafer2210. Additionally, an anti-punch-through ion implantation is performedwith n-type dopants, and a threshold-adjustment ion implantation isperformed also with n-type dopants.

In one embodiment, the following processes are performed:

-   -   AA Nitride Removal (50:1 HF 60 seconds and 175° C. H₃PO₄ 60        minutes)    -   Measure remain oxide thickness <120 Å/Pad oxide Removal (50:1 HF        2.5 minutes, E/R=55 Å/minute)    -   SACRIFICE OXIDE DEPOSITION (Dry 110 Å, 920° C., 45 minutes, O₂)

For example, the following additional processes are performed for NMOStransistor:

-   -   P-Well Photo (PW/AA overlay ±0.1 μm)    -   P-Well Implant: P-well B11 (specie B⁺, energy 160 KeV, dosage        1.5×10¹³ ions/cm², tilt 0)    -   N-APT Implant: N-APT B11 (specie B⁺, energy 25 KeV, dosage        5.5×10¹² ions/cm², tilt 0)    -   VTN Implant: VT IMP In115 (specie In⁺, energy 170 KeV, dosage        7.0×10¹² ions/cm², tilt 0)

In another example, the following additional processes are performed forPMOS transistor:

-   -   N-Well Photo (NW/OD overlay ±0.1 μm)    -   N-well Implant: N-well P31 (specie P⁺, energy 440 KeV, dosage        1.5×10¹³ ions/cm², tilt 0)    -   P-APT Implant: P-APT P31 (specie P⁺, energy 140 KeV, dosage        1.5×10¹² ions/cm², tilt 0)    -   VTP Implant: VTP A75 (specie As⁺, energy 130 KeV, dosage        1.1×10¹³ ions/cm², tilt 0)

At the process 2120, one or more gate regions are formed for splitting.FIGS. 4(A) and (B) show a simplified method for forming gate region forsplitting for making split dual gate field effect transistor accordingto an embodiment of the present invention. These diagrams are merelyexamples, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications.

As shown in FIGS. 4(A) and (B), the oxide layer 2310 is removed, andanother oxide layer 2410 is deposited on the wafer 2210. On the oxidelayer 2410, a polysilicon layer 2420 is formed. Afterwards, thepolysilicon layer 2420 is partially etched to form polysilicon gateregions 2430 and 2432. The polysilicon gate regions 2430 and 2432 arethen partially oxidized under certain conditions.

In one embodiment, the following processes are performed:

-   -   SAC Oxide Removal    -   Gate Oxide Deposition (750° C., Wet O₂; 900° C. anneal; 32±2 Å)    -   POLY Deposition (620° C. 2000 Å, Undoped poly/crystallized flat        poly)    -   DARC DEPOSITION (DARC, 320 Å, He based)    -   POLY PHOTO (DUV scanner, 0.18±0.015 μm; Overlay (Poly        Gate/AA=±0.07 μm))    -   Poly Gate Etch: 1. Hard bake; 2. Poly etch; 3. polymer dip        (100:1 HF 10 seconds); 4. PR strip; 5. AEI/CD (0.18±0.015        μm); 6. Oxide thickness measure (Trench OXIDE 3550±600 Å, Oxide        on Active Area >10 Å); 7. SiON mask remove (50:1 HF 5 seconds,        and H₃PO₄ 7 minutes)    -   Poly Re_Oxidation (1000° C., RTO 20±4 Å for etch damage        recovery).

At the process 2125, one or more LDD regions and one or more spacerregions are formed. FIG. 5 shows a simplified method for forming LDDregion and spacer region for making split dual gate field effecttransistor according to an embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications.

As shown in FIG. 5, one or more ion implantation processes are performedto form one or more LDD regions. For example, the LDD regions 2510 and2520 are p-type doped for PMOS. In another example, the LDD regions 2530and 2540 are n-type doped for NMOS. Additionally, one or more spacersare formed. For example, each of the spacers 2550, 2560, 2570, and 2580includes a nitride layer sandwiched between two oxide layers.

In one embodiment, the following processes are performed:

-   -   NLL PHOTO (e.g., 1.8V device) (In-line monitor OVERLAY/CD)    -   PLL PHOTO (e.g., 1.8V device) (In-line monitor OVERLAY/CD)    -   ONO Spacer DEPOSITION (In-line monitor ONO THICKNESS)    -   Spacer ETCH (In-line monitor remaining OXIDE THICKNESS and STI        OXIDE THICKNESS)

At the process 2130, one or more heavily doped source regions and one ormore heavily doped drain regions are formed. FIG. 6 shows a simplifiedmethod for forming heavily doped source region and heavily doped drainregion for making split dual gate field effect transistor according toan embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications.

As shown in FIG. 6, one or more ion implantation processes are performedto form one or more heavily doped source regions and heavily doped drainregions. For example, the formed regions 2610 and 2620 are doped to p+for PMOS. In another example, the formed regions 2630 and 2640 are dopedto n+ for NMOS.

In one embodiment, the following processes are performed:

-   -   N+S/D Photo Mask    -   Overlay (N+/AA=±0.12 μm)    -   N+ S/D Implant: 1. specie As⁺, energy 60 KeV, dosage 5.5×10¹⁵        ions/cm², tilt 0; 2. specie P⁺, energy 35 KeV, dosage 1.5×10¹⁴        ions/cm², tilt 0    -   N+ S/D RTA anneal (1025° C., 20 seconds, N₂)    -   P+ S/D Photo Mask    -   Overlay (P+/AA=±0.12 μm)    -   P+ S/D Implant: 1. specie B⁺, energy 5 KeV, dosage 3.5×10¹³        ions/cm², tilt 0; 2. specie    -   B⁺, energy 15 KeV, dosage 3.0×10¹³ ions/cm², tilt 0

At the process 2135, split dual gates are formed. FIGS. 7(A), (B), and(C) show a simplified method for forming split dual gates for makingsplit dual gate field effect transistor according to an embodiment ofthe present invention. FIG. 7(B) is a simplified cross-section along Band B′, and FIG. 7(C) is a simplified cross-section along C and C′.These diagrams are merely examples, which should not unduly limit thescope of the claims. One of ordinary skill in the art would recognizemany variations, alternatives, and modifications.

As shown in FIGS. 7(A), (B), and (C), part of the polysilicon gateregion 2430 is removed. As a result, dual gate regions 2710 and 2720 areformed. Additionally, the dual gate regions 2710 and 2720 are separatedby a gap 2730, such an air gap. In another example, similar dual gateregions are formed by removing part of the polysilicon gate region 2432.

In one embodiment, the following processes are performed:

-   -   PSDG POLY PHOTO (DUV scanner, Overlay (PSDG/AA=±0.07 μm))    -   PSDG Poly Gate Etch: 1. Hard bake; 2. Poly etch; 3. polymer dip        (100:1 HF 10 seconds); 4. PR strip; 5. AEI.

In another embodiment, the following processes are performed to form thedual gate regions 2710 and 2720:

-   -   Polysilicon photolithography. For example: DUV scanner,        0.3±0.015 μm; Overlay (Poly Gate/AA=±0.07 μm).    -   Polysilicon etching. For example: 1. Hard bake; 2. Poly etch; 3.        polymer dip (100:1 HF 10 seconds); 4. PR strip; 5. AEI/CD        (0.3±0.015 μm); 6. Measure Oxide thickness on Active Area (>10        Å)

At the process 2140, one or more salicide layers are formed. FIGS. 8(A),(B), and (C) show a simplified method for forming salicide layer andinsulation layer for making split dual gate field effect transistoraccording to an embodiment of the present invention. FIG. 8(B) is asimplified cross-section along B and B′, and FIG. 8(C) is a simplifiedcross-section along C and C′. These diagrams are merely examples, whichshould not unduly limit the scope of the claims. One of ordinary skillin the art would recognize many variations, alternatives, andmodifications.

As shown in FIGS. 8(A), (B), and (C), salicide layers 2810 and 2820 areformed on the dual gate regions 2710 and 2720. Additionally, at leastsalicide layers 2812 and 2814 are formed on the wafer 2210.Additionally, within the gap 2730, an insulation layer 2822 is formed.For example, the insulation layer 2822 includes a salicide block layer(SAB), such as an silicon-rich oxide layer. In another example, theinsulation layer 2822 includes an insulation material, such as siliconoxide, silicon nitride, and/or silicon oxynitride. In yet anotherexample, the insulation layer 2822 and the remaining part of the gap2730 form an insulation region that separates the dual gate regions 2710and 2720. In yet another example, similar salicide layers and insulationlayer are formed for dual gate regions made from the polysilicon gateregion 2432.

In one embodiment, the following processes are performed:

-   -   Salicide Block OXIDE DEPOSITION (SiON 350 Å)    -   S/D RTA Anneal (1015° C., 10 seconds, N₂)    -   SAB PHOTO (OVERLAY to AA, SAB/AA=±0.07 μm)    -   SAB ETCH (Dry and Wet NDH110A)    -   Co_Wet Pre_Clean (Wet NDH25A: Chemical 49% HF: H₂O (1:100),        temperature 22.5° C. ˜23.5° C., 60 seconds)    -   Salicide Co DEPOSITION (Pre-clean RF 150 W and remove oxide 30        Å, deposition Cobalt 85 Å)    -   Salicide TiN DEPOSITION (Cap 200 Å)    -   RTA1/Selective    -   Wet Etch/RTA2 (RTA1: 500° C.; RTA2: 850° C.)

In another embodiment, to form the insulation layer 2822, aphotolithography is performed to pattern the SAB layer. The SAB photomask is aligned to Active Area (AA) layer mark, for example, OVERLAYSAB/AA=±0.07 μm. After the photolithography, the SAB layer is etched byplasmas dry etch and then wet etch. For example, the wet etch processuses the chemical 49% HF: H₂O (1:100) solvent at the temperature of22.5° C.˜23.5° C. for 270 seconds.

At the process 2145, one or more inter-layer dielectric layer is formed.FIG. 9 shows a simplified method for forming inter-layer dielectriclayer for making split dual gate field effect transistor according to anembodiment of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications.

As shown in FIG. 9, a silicon oxynitride layer 2910 is formed to coverat least part of the structure that results from the process 2140.Additionally, a BPSG layer 2920 is deposited on the silicon oxynitridelayer 2910 and undergoes a reflow process. On the BPSG layer 2920, anoxide layer 2930 is formed and planarized by a CMP process.

In one embodiment, the following processes are performed:

-   -   PE-SION DEPOSITION (400 Å ETCH Stop Layer)    -   Scrubber Clean    -   BPSG DEPOSITION/Reflow/CR Clean (2K/0650BPF30M)    -   PETEOS DEPOSITION (10.5 KÅ)    -   Oxide CMP for ILD (Post CMP THICKNESS 7.5 KÅ±1 KÅ)

At the process 2150, one or more contact layers are formed. FIG. 10shows a simplified method for forming contact layer for making splitdual gate field effect transistor according to an embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications.

As shown in FIG. 10, one or more contact holes are formed. For example,contact holes 3010 and 3020 expose the salicide layer 2814 and thesalicide layer on the polysilicon gate region 2432. In one embodiment,the polysilicon gate region 2432 is etched to become dual gate regionsat the process 2135. In another embodiment, the polysilicon gate region2432 is not etched to become dual gate regions at the process 2135. Inthe contact holes, a layer 3030 is formed to cover the bottom surfacesand side surfaces. For example, the layer 3030 includes Ti and TiN.Afterwards, the contact holes are filled by tungsten material 3040.

In one embodiment, the following processes are performed:

-   -   CONTACT_PHOTO DARC (Oxide 200 Å and SiON 600 Å)    -   CONTACT PHOTO (OVERLAY/CD: ±0.045 μm, 0.235 μm)    -   CONTACT ETCH (0.235 μm)    -   CONTACT Glue layer (Pre-clan 100 Å, Ti 200 Å, TiN 1×50 Å) Glue        Anneal (0690RTA60S)    -   Tungsten Plug (W) DEPOSITION (W3.3 KÅ bulk deposition 415° C.)

At the process 2155, one or more metal layers are formed. FIGS. 11(A)and (B) show a simplified method for forming metal layer for makingsplit dual gate field effect transistor according to an embodiment ofthe present invention. These diagrams are merely examples, which shouldnot unduly limit the scope of the claims. One of ordinary skill in theart would recognize many variations, alternatives, and modifications.

As shown in FIGS. 11 (A) and (B), one or more metal layers are formed.For example, a metal layer 3110 is in contact with the contact holes3010 and 3020 filled with the tungsten material 3040. In anotherexample, at least one of the additional metal layers 3120, 3130, 3140,3150, and 3160 are also formed. The different metal layers are separatedby at least an inter-metal dielectric layer. The inter-metal dielectriclayer is punched through to form one or conductive plugs, which provideconductive connections between the metal layers.

In one embodiment, the following processes are performed to form a metallayer:

-   -   METAL1 Sputter (Ti/TiN/AlCu/Ti/TiN: THICKNESS 100 Å/200 Å/4        KÅ/50 Å/300 Å) (for example, Ti for better TiO₂ adhesion; in        another example, TiN to prevent TiAl₃)    -   Scrubber    -   METAL1_PHOTO DARC (320 Å SiON)    -   Scrubber    -   METAL1 PHOTO (0.22±0.015)    -   METAL1 ETCH (0.24±0.02)

In another embodiment, at least the following additional processes areperformed to form additional metal layers:

-   -   IMD Linear OX DEPOSITION(SRO 500 Å)    -   IMD HDP FGS OX (SRO_(—)100 Å and 6 KÅ)    -   IMD PEFSG OX (11.5 KÅ)    -   IMD CMP (Post THICKNESS 6.5 KÅ±1.2 KÅ)    -   USG DEPOSITION (2 KÅ)    -   VIA1˜Top Via PHOTO (0.26 μm, 0.39 μm)    -   VIA1˜Top Via ETCH (0.26 μm, 0.39 μm)    -   M2˜TOP Metal PHOTO (0.26 μm, 0.49 μm)    -   M2˜TOP Metal ETCH (0.28 μm, 0.51 μm)

At the process 2160, one or more passivation layers are formed. FIG. 12shows a simplified method for forming passivation layer for making splitdual gate field effect transistor according to an embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications.

As shown in FIG. 12, one or more passivation layers are formed. Forexample, an oxide layer 3210 is formed on at least a metal layer, suchas the metal layer 3160. In another example, a nitride layer 3220 isalso formed on the oxide layer 3210.

In one embodiment, the following processes are performed to form a metallayer:

-   -   Passivation HDP Oxide DEPOSITION 10 KÅ    -   Passivation Nitride DEPOSITION 6 KÅ

FIGS. 13(A) and (B) show a simplified method for making split dual gatefield effect transistor according to another embodiment of the presentinvention. This diagram is merely an example, which should not undulylimit the scope of the claims herein. The method 3300 includes some orall of the 168 processes. Although FIGS. 13(A) and (B) have been shownusing a selected sequence of processes, there can be many alternatives,modifications, and variations. For example, some of the processes may beexpanded and/or combined. Other processes may be inserted to those notedabove. Depending upon the embodiment, the specific sequence of processesmay be interchanged with others replaced. Some of the processes may beexpanded and/or combined, and/or other processes may be inserted tothose noted above.

According to yet another embodiment of the present invention, a methodfor making a semiconductor device with at least two gate regionsincludes providing a substrate region including a surface. Additionally,the method includes forming a source region in the substrate region byat least implanting a first plurality of ions into the substrate regionand forming a drain region in the substrate region by at leastimplanting a second plurality of ions into the substrate region. Thedrain region and the source region are separate from each other.Moreover, the method includes depositing a gate layer on the surface andforming a first gate region and a second gate region on the surface. Theforming a first gate region and a second gate region includes forming aninsulation region on the surface by at least removing a part of the gatelayer, and the first gate region and the second gate region areseparated by the insulation region. The first gate region is capable offorming a first channel in the substrate region, and the first channelis from the source region to the drain region. The second gate region iscapable of forming a second channel in the substrate region, and thesecond channel is from the source region to the drain region. Forexample, the method is implemented according to the method 2100 and/orthe method 3300.

According to yet another embodiment of the present invention, a methodfor making a semiconductor device with at least two gate regionsincludes providing a substrate region including a surface. Additionally,the method includes forming a source region in the substrate region byat least implanting a first plurality of ions into the substrate region,and forming a drain region in the substrate region by at leastimplanting a second plurality of ions into the substrate region. Thedrain region and the source region are separate from each other.Moreover, the method includes depositing a gate layer on the surface andforming a first spacer region. The first spacer region is in contactwith the gate layer. Also, the method includes forming a second spacerregion, and the second spacer region is in contact with the gate layer.Additionally, the method includes removing at least a part of the gatelayer to form a first gate region, a second gate region, and aninsulation region on the surface. The first gate region and the secondgate region are separated by the insulation region. For example, themethod is implemented according to the method 2100 and/or the method3300.

According to yet another embodiment of the present invention, a methodfor making a semiconductor device with at least two gate regionsincludes providing a substrate region including a surface. Additionally,the method includes forming a source region in the substrate region byat least implanting a first plurality of ions into the substrate region,and forming a drain region in the substrate region by at leastimplanting a second plurality of ions into the substrate region. Thedrain region and the source region are separate from each other.Moreover, the method includes depositing a gate layer on the surface,and forming a first spacer region. The first spacer region is in contactwith the gate layer. Also, the method includes forming a second spacerregion, and the second spacer region is in contact with the gate layer.Additionally, the method includes removing at least a part of the gatelayer to form a first gate region, a second gate region, and aninsulation region on the surface. The first gate region and the secondgate region are separated by the insulation region. The first gateregion is associated with a first channel related to a first channellength, and the first channel length is equal to or shorter than 200 nm.The insulation region is associated with a width in a direction from thefirst gate region to the second gate region, and the width ranges from10 nm to 10,000 nm. For example, the method is implemented according tothe method 2100 and/or the method 3300.

FIG. 14 is a simplified diagram for split dual gate field effecttransistor according to an embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. For example, the device 100is made according to the method 2100. In another example, the device 100is made according to the method 3300. The device 100 includes thefollowing components:

-   -   1. Substrate region 110;    -   2. Source region 120;    -   3. Drain region 130;    -   4. Gate regions 140 and 150;    -   5. Insulation region 160;    -   6. Spacer regions 170 and 172;    -   7. Gate dielectric region 180.

Although the above has been shown using a selected group of componentsfor the device 100, there can be many alternatives, modifications, andvariations. For example, some of the components may be expanded and/orcombined. Other components may be inserted to those noted above.Depending upon the embodiment, the arrangement of components may beinterchanged with others replaced. For example, the device 100 is anNMOS transistor. In another example, the device 100 is a PMOStransistor. Further details of these components are found throughout thepresent specification and more particularly below.

In one embodiment, the substrate region 110 is made of a semiconductormaterial. For example, the semiconductor material is silicon. Thesemiconductor substrate region 110 is intrinsic or doped to p-type orn-type. For example, the substrate region 110 is doped to p-type, with adopant concentration ranging from 1.0×10¹⁵ cm⁻³ to 2.0×10¹⁵ cm⁻³. Inanother example, the substrate region 110 is doped to n-type, with adopant concentration ranging from 1.0×10¹⁵ cm⁻³ to 2.0×10¹⁵ cm⁻³.

The source region 120 and the drain region 130 are doped to n-type orp-type. For example, the source region 120 is doped to n-type with adopant concentration ranging from 1.0×10¹⁸ cm⁻³ to 1.0×10¹⁹ cm⁻³, andthe drain region 130 is doped to n-type with a dopant concentrationranging from 1.0×10¹⁸ cm⁻³ to 1.0×10¹⁹ cm⁻³. In another example, thesource region 120 is doped to p-type with a dopant concentration rangingfrom 1.0×10¹⁸ cm⁻³ to 1.0×10¹⁹ cm⁻³, and the drain region 130 is dopedto p-type with a dopant concentration ranging from 1.0×10¹⁸ cm⁻³ to1.0×10¹⁹ cm⁻³.

The gate dielectric region 180 is located on the top surface 112 of thesubstrate region 110. For example, the gate dielectric region 180 ismade of silicon oxide, silicon nitride, silicon oxynitride, or anycombination thereof. In another example, the gate dielectric region is adielectric layer. The gate regions 140 and 150 and the insulation region160 are located on the gate dielectric region 180. For example, the gateregions 140 and 150 each are made of polysilicon. As shown in FIG. 14,the gate regions 140 and 150 are not in direct contact with each otherbut are separated by the insulation region 160. For example, theinsulation region 160 has two side surfaces, one of which is in directcontact with the gate region 140 and the other one of which is in directcontact with the gate region 150. In another example, the insulationregion 160 includes a gap, such as an air gap. In yet another example,the insulation region 160 includes silicon oxide, silicon nitride,silicon oxynitride, or any combination thereof. In yet another example,the insulation region 160 includes SAB.

The spacer regions 170 and 172 are located on the top surface 112. Thespacer region 170 is in direct contact with the gate regions 140 and 150and the insulation region 160 on one side, and the spacer region 172 isin direct contact with the gate regions 140 and 150 and the insulationregion 160 on another side. For example, the spacer regions 170 and 172each are made of silicon oxide, silicon nitride, silicon oxynitride, orany combination thereof.

FIG. 15 is a simplified top-view layout diagram for split dual gatefield effect transistor according to another embodiment of the presentinvention. This diagram is merely an example, which should not undulylimit the scope of the claims. One of ordinary skill in the art wouldrecognize many variations, alternatives, and modifications. The device100 includes at least the source region 120, the drain region 130, thegate regions 140 and 150, and the insulation region 160. Although theabove has been shown using a selected group of components for the device100, there can be many alternatives, modifications, and variations. Forexample, some of the components may be expanded and/or combined. Othercomponents may be inserted to those noted above. Depending upon theembodiment, the arrangement of components may be interchanged withothers replaced. Further details of these components are foundthroughout the present specification and more particularly below.

As shown in FIG. 15, the gate regions 140 and 150 are separated by theinsulation region 160. The gate regions 140 and 150 and the insulationregion 160 form a continuous region, and the continuous region separatesthe source region 120 and the drain region 130 in the top view. The gateregion 140 includes side surfaces 142 and 144, the gate region 150includes side surfaces 152 and 154, and the insulation region 160includes side surfaces 162 and 164. For example, the side surfaces 142,152, and 162 form a continuous surface, and the side surfaces 144, 154,and 164 form another continuous surface. In another example, the sourceregion 120 is aligned with the side surfaces 142, 152, and 162. In yetanother example, the drain region 130 is aligned with the side surfaces144, 154, and 164.

The source region 120 has a width 124, and the drain region 130 has awidth 134. For example, the width 124 ranges from 10 nm to 20,000 nm. Inanother example, the width 134 ranges from 10 nm to 10,000 nm. In oneembodiment, the widths 124 and 134 are the same. In another embodiment,the widths 124 and 134 are different. The gate region 140 has a length146, and the gate region 150 has a length 156. For example, the length146 ranges from 10 nm to 1,000 nm. In another example, the length 156ranges from 10 nm to 1,000 nm. In one embodiment, the lengths 146 and156 are the same. In another embodiment, the lengths 146 and 156 aredifferent. The gate region 140 has a width 148, the gate region 150 hasa width 158, and the insulation region 160 has a width 168. For example,the total width for the width 148, the width 158, and the width 168 isequal to the width 124 and/or the width 134. In another example, thewidth 148 ranges from 10 nm to 15,000 nm. In yet another example, thewidth 158 ranges from 10 nm to 15,000 nm. In yet another example, thewidth 168 ranges from 10 nm to 15,000 nm. In yet another example, thewidth 168 ranges from 10 nm to 10,000 nm. In one embodiment, the widths148 and 158 are the same. In another embodiment, the widths 148 and 158are different.

As shown in FIGS. 14 and 15, the gate regions 140 and 150 are physicallyseparated by the insulation region 160 according to an embodiment of thepresent invention. For example, the gate regions 140 and 150 can bebiased to different voltage levels. In another embodiment, the gateregion 140 with proper bias can form a channel from the source region120 to the drain region 130 in the substrate region 110, and the gateregion 150 with proper bias can form another channel from the sourceregion 120 to the drain region 130 in the substrate region 110. Forexample, the channel under the gate region 140 has a length 146, and thechannel under the gate region 150 has a length 156.

The present invention has various advantages. Some embodiments of thepresent invention provide a new method for making a new planar splitdual gate transistor device. Certain embodiments of the presentinvention provide a method for making dual gates that can be biasedindependently. For example, the independent gate biases can providedynamical control of the device characteristics such as thresholdvoltage, sub-threshold swing, and/or the saturation drain current. Someembodiments of the present invention can be used to make a device thatsignificantly reduces transistor leakage current. Certain embodiments ofthe present invention provide a method for making a device that hasadjustable threshold voltage without varying gate oxide thickness ordoping profile.

It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this applicationand scope of the appended claims.

1-21. (canceled)
 2. A method for making a semiconductor device with atleast two gate regions, the method comprising: providing a substrateregion including a surface; forming a source region in the substrateregion by at least implanting a first plurality of ions into thesubstrate region; forming a drain region in the substrate region by atleast implanting a second plurality of ions into the substrate region,the drain region and the source region being separate from each other;depositing a gate layer on the surface; forming a first spacer region,the first spacer region being in contact with the gate layer; forming asecond spacer region, the second spacer region being in contact with thegate layer; removing at least a part of the gate layer to form a firstgate region, a second gate region, and an insulation region on thesurface; wherein the first gate region and the second gate region areseparated by the insulation region.
 3. The method of claim 2 wherein theremoving at least a part of the gate layer includes depositing aninsulating material, the insulation region includes at least theinsulating material.
 4. The method of claim 2 wherein: the first gateregion is capable of forming a first channel in the substrate region,the first channel from the source region to the drain region; the secondgate region is capable of forming a second channel in the substrateregion, the second channel from the source region to the drain region.5. A method for making a semiconductor device with at least two gateregions, the method comprising: providing a substrate region including asurface; forming a source region in the substrate region by at leastimplanting a first plurality of ions into the substrate region; forminga drain region in the substrate region by at least implanting a secondplurality of ions into the substrate region, the drain region and thesource region being separate from each other; depositing a gate layer onthe surface; forming a first spacer region, the first spacer regionbeing in contact with the gate layer; forming a second spacer region,the second spacer region being in contact with the gate layer; removingat least a part of the gate layer to form a first gate region, a secondgate region, and an insulation region on the surface; wherein: the firstgate region and the second gate region are separated by the insulationregion; the first gate region is associated with a first channel relatedto a first channel length, the first channel length being equal to orshorter than 200 nm; the insulation region is associated with a width ina direction from the first gate region to the second gate region, thewidth ranging from 10 nm to 10,000 nm.
 6. The method of claim 5 wherein:the second gate region is associated with a second channel; the firstchannel and the second channel are not in contact to each other.